Wireless communications systems and related networks, such as Universal Mobile Telecommunications Systems (UMTSs), are increasingly deploying Fourth Generation (4G), its offspring Long Term Evolution (LTE), and 5th Generation New Radio (5G-NR) described and being developed by the Third Generation Partnership Project (3GPP) to support higher data rates. At the same time, wireless communications systems continue to use older Second Generation (2G) and Third Generation (3G) modes throughout the world. In order to support multiple standards efficiently, mobile devices have need for programmable, low-power, low-cost, highly integrated transceivers compatible with the corresponding cellular technologies. Therefore, analog to digital converters (ADCs) used in such transceivers are also required to be flexible and optimizable in terms of resolution, bandwidth, and power consumption (depending upon the wireless communications standard or mode).
Delta-sigma modulator architecture has become a preferred ADC solution due to its easy re-configurability for better performance or less power consumption by changing an oversampling ratio (OSR) of an ADC circuit. The delta-sigma architecture is less dependent on analog component values and its noise shaping property helps attenuate a significant amount of quantization noise and out of band interferers.
Several continuous-time (CT) and discrete-time (DT) delta-sigma modulators have been proposed supporting multiple communications standards (e.g., modes of operation). While CT delta-sigma modulators have certain advantages over DT delta-sigma modulators, such as implicit anti-aliasing filtering and power efficiency, CT delta-sigma modulators are more prone to non-idealities such as clock jitter, excess loop delay, and integrator coefficient (RC time constant) variation which can be as high as ±%20. Furthermore, multi-mode CT delta-sigma modulators are more sensitive to parasitic effects and are more complex because CT loop filters are designed for a single operating clock frequency, and they need multiple switchable passive resistor-capacitor (RC) combinations in order to satisfy multi-mode operation. Comparatively, DT modulators are robust with respect to process variations as their transfer functions rely on capacitor ratios. Furthermore, multi-mode operation can be realized by adjusting clock frequency. However, active DT delta-sigma modulators consume much more power compared to their CT counterparts due to the use of operational transconductance amplifiers (OTAs) having higher unity gain bandwidth (UGBW) requirements. The UGBW of the OTAs used in active DT modulators needs to be much higher than the sampling frequency to ensure proper settling in switched capacitor integrators. Compared to active delta-sigma modulators, passive delta-sigma modulators provide lower power solutions for DT operation due to the elimination of power hungry OTAs. Nevertheless, the resolution of passive delta-sigma modulators can be limited due to limited options for reducing quantization noise power.